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Transaction level modelling ?

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archive over 18 years ago

Hi , I have confusion regarding transaction level modelling.can someone explain it with an example? what exactly is transaction level modelling & how it can be achieved using system verilog? -thanks -Manmohan


Originally posted in cdnusers.org by mssajwan
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    archive over 18 years ago

    Transaction-level models (TLMs) are architecture models that exchange transactions, i.e. abstract data structures, instead of signals. This means that instead of having to toggle hundreds of signals to perform a data write on a bus, this operation is encapsulated in a data structure and communicated to an abstract representation (TLM) of the bus, hence completing the transaction a lot faster, but sacrificing at the same time a certain degree of accuracy.

    TLMs are mostly used for rapid prototyping, performance analysis and could serve as "golden" models for your RTL verification. There are usually several abstraction levels for implementing a TLM according to your needs, such as un-timed models, cycle-accurate and even pin-accurate models. The more elaborate the abstraction layer, the more simulation time it will consume, so the performance can end up being comparable to RTL simulation.

    To implement TLM, it is usually not a question of language, as most modern languages support this, but a question of methodology. Ideally, you would want to transition from the TLM environment to a RTL environment, simply by adding BFMs and monitors that translate the transactions from/to signals, while keeping the rest of the environment intact. uRM offers a lot of information on how to achieve this, even in mixed-language environments.


    Originally posted in cdnusers.org by iraklis
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  • archive
    archive over 18 years ago

    Transaction-level models (TLMs) are architecture models that exchange transactions, i.e. abstract data structures, instead of signals. This means that instead of having to toggle hundreds of signals to perform a data write on a bus, this operation is encapsulated in a data structure and communicated to an abstract representation (TLM) of the bus, hence completing the transaction a lot faster, but sacrificing at the same time a certain degree of accuracy.

    TLMs are mostly used for rapid prototyping, performance analysis and could serve as "golden" models for your RTL verification. There are usually several abstraction levels for implementing a TLM according to your needs, such as un-timed models, cycle-accurate and even pin-accurate models. The more elaborate the abstraction layer, the more simulation time it will consume, so the performance can end up being comparable to RTL simulation.

    To implement TLM, it is usually not a question of language, as most modern languages support this, but a question of methodology. Ideally, you would want to transition from the TLM environment to a RTL environment, simply by adding BFMs and monitors that translate the transactions from/to signals, while keeping the rest of the environment intact. uRM offers a lot of information on how to achieve this, even in mixed-language environments.


    Originally posted in cdnusers.org by iraklis
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