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Transaction level modelling ?

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Hi , I have confusion regarding transaction level modelling.can someone explain it with an example? what exactly is transaction level modelling & how it can be achieved using system verilog? -thanks -Manmohan


Originally posted in cdnusers.org by mssajwan
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  • Hi Manmohan,

    I am not aware of a SystemVerilog TLM example, but the Incisive Plan to Closure Methodology (IPCM) offers a TLM example in SystemC, which you might find interesting as a starting point. Apart from useful documentation, you will also find extensive code examples that highlight the TLM principles. If possible, I strongly recommend you to consider SystemC as a modeling language, as it was designed purely for that purpose.

    If anyone is aware of a SystemVerilog TLM example, please let us know.


    Originally posted in cdnusers.org by iraklis
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  • Hi Manmohan,

    I am not aware of a SystemVerilog TLM example, but the Incisive Plan to Closure Methodology (IPCM) offers a TLM example in SystemC, which you might find interesting as a starting point. Apart from useful documentation, you will also find extensive code examples that highlight the TLM principles. If possible, I strongly recommend you to consider SystemC as a modeling language, as it was designed purely for that purpose.

    If anyone is aware of a SystemVerilog TLM example, please let us know.


    Originally posted in cdnusers.org by iraklis
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