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Generate - When not taken

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Question: If you had the code snippet below and the value of the local parameter NUMOFMASTERS is 0, is it really an error for the L_blocken and cfg_blocken signals to not be declared. Since the generate does not actually activate any code it would seem that the signal declaration would not be required. // Flops unique to the Master Logic generate if (NUMOFMASTERS > 0 ) always_ff @(posedge Clk_foo) begin if(!Reset_l_foo)begin L_blocken


Originally posted in cdnusers.org by bryan

  • Yes, it is required. Since parameter values can be overridden, the parser will process the code and save it in case the instantiation overrides the default parameter values and the generate statements are executed.


    Originally posted in cdnusers.org by TAM

  • Not to split hairs but it was my understanding that local parameters (localparam) could not be overriden per instance. Would I have the same error message if I used a constant? Or is this just the way the generate works? A LRM reference to help clarify this would be appreciated.


    Originally posted in cdnusers.org by bryan

  • Of course, you are right. Localparams cannot be directly overridden. But they are very often derived from actual parameters which can change values. So I don't think that the compiler can assume that the value can never occur.

    parameter tagw = 8;
    parameter cmdw = 4;
    localparam opw = tagw + cmdw;

    I suppose we know that "localparam numofmasters = 0;" would be a constant that couldn't be overridden, but apparently the language parser doesn't analyze it to that depth.

    I can't quote anything in the LRM that talks specifically about the interpretation of a generate block's contents when the conditions are not satisfied, except that it does require that the contents of a generate scope have to be legal Verilog.

    Can you declare the signals inside the generate loop? That way those who need them will see them and those who do not will not.


    Originally posted in cdnusers.org by TAM

  • I believe that signals declared within a generate are scoped to the generate. If true that would seem to say no to your question. Also our coding style is to declare all signals at the top of the file and then put all the code at the bottom. Inline declarations would not also us to conform to that practice.

    I really looking for a LRM based answer so I can decide if this is a tool issue or just the way that generates are interpreted.


    Originally posted in cdnusers.org by bryan

  • Posted By bryan on 2/26/2007 3:04 PM
    I believe that signals declared within a generate are scoped to the generate. If true that would seem to say no to your question. Also our coding style is to declare all signals at the top of the file and then put all the code at the bottom. Inline declarations would not also us to conform to that practice.

    I really looking for a LRM based answer so I can decide if this is a tool issue or just the way that generates are interpreted.
    Clause 12.4 of the Verilog LRM 2005 states

    "Generate schemes are evaluated during elaboration of the model. Elaboration occurs after parsing the HDL and before simulation; ..."

    Statements within the generate block must therefore all be syntactically correct - the compiler should give an error if it encounters illegal code (such as use of undeclared signals), even if the generate block is subsequently skipped during elaboration.

    Regards,
    Dave



    Originally posted in cdnusers.org by dl_doulos

  • Thanks. Now I have a good test for a linter. Do I get a signal not used message if I declare the signals for this example........


    Originally posted in cdnusers.org by bryan

  • Do I get a signal not used message if I declare the signals for this example........

    I do not believe the LRM places any obligation on a tool to give a warning about nets or variables that are unused as a result of a generate block not being elaborated. On the other hand, it is a perfectly reasonable thing to ask for if you are developing a linter.

    Regards,
    Dave


    Originally posted in cdnusers.org by dl_doulos

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