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DPI and Classes

archive
archive over 18 years ago

I'm using the DPI to instantiate and run our firmware and have a problem when the firmware tries to call exported tasks.

I cannot seem to do an export on a class tasks so I have to declare my export tasks outside of the class.

However, I don't know how to call the class member task (which is what I really want) from these outside tasks.


This is my code.  I've tried hierarchical names to get the the write and read member tasks in the driver but get the following error from ncvlog:

  test.prgm.sys.spi.drv.read(address, data);
                                                 |
ncvlog: *E,ILLHIN (../tb/spi/spi_driver.sv,52|49): illegal location for a hierarchical name (in a package).

-------------------------------------------

export

"DPI-C" SV_spi_read = task spi_read;
export "DPI-C" SV_spi_write = task spi_write;

class spi_driver;
extern function new;
extern task write;
extern task read;
endclass : spi_driver

function spi_driver::new;
$display("spi_driver::new()");
endfunction : new

task spi_driver::write(input byte address, input byte data);
$display("spi_write of %x to address %x", data, address);
endtask : write

task spi_driver::read( input byte address, output byte data);;
$display("spi_read of address %x", address);
endtask : read



/////////////////////////////////////////////////////////////
//
// I cannot figure out how to export a class member task to the DPI so
// these two functions are stand-alone functions.
//
task spi_read( input byte address, output byte data);
$display("spi_read of address %x", address);
spi_driver
::spi_read(Address, data);  // I don't know how to call class member from here.
endtask
: spi_read

task spi_write(input byte address, input byte data);
$display("spi_write of %x to address %x", data, address);
spi_driver
::spi_write(Address, data);  // I don't know how to call class member from here.
endtask : spi_write

----------------------------
Originally posted in cdnusers.org by dfechser
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  • archive
    archive over 18 years ago

    Hi,

    We now have a product called Incisive Software Extensions (ISX) which, reading between the lines of your request, might be of interest, though it does not directly answer your System Verilog question. 

    ISX provides a mechanism to build a link between an advanced verification environment and your embedded software so that you can call embedded software functions and drive and monitor embedded software variables from the verification environment. The main difference between this and what you are doing right now is that ISX will maintain this interface capability irrespective of the Processor model kind, i.e. you can run it on you firmware compiled for the workstation as you are doing right now, and you can still use it when the embedded software is running on a processor model in the simulation, even if the model is an abstract ISS (Instruction Set Simulator) or the final RTL. We can even link to it if the design including the processor and software resides on an Accelerator or Emulator. 

    If you are interested to learn more about ISX please fell free to drop me a mail at giles@cadence.com 

    Best regards

    Giles


    Originally posted in cdnusers.org by giles
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  • archive
    archive over 18 years ago

    Hi,

    We now have a product called Incisive Software Extensions (ISX) which, reading between the lines of your request, might be of interest, though it does not directly answer your System Verilog question. 

    ISX provides a mechanism to build a link between an advanced verification environment and your embedded software so that you can call embedded software functions and drive and monitor embedded software variables from the verification environment. The main difference between this and what you are doing right now is that ISX will maintain this interface capability irrespective of the Processor model kind, i.e. you can run it on you firmware compiled for the workstation as you are doing right now, and you can still use it when the embedded software is running on a processor model in the simulation, even if the model is an abstract ISS (Instruction Set Simulator) or the final RTL. We can even link to it if the design including the processor and software resides on an Accelerator or Emulator. 

    If you are interested to learn more about ISX please fell free to drop me a mail at giles@cadence.com 

    Best regards

    Giles


    Originally posted in cdnusers.org by giles
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