interface for bidirectional pins

Hello,

You will have to treat the wire in the interface like you would treat any wire in Verilog. It can only have one driver at a time. I believe you will have to conditionally assign reg_name:

assign my_if.biDir_pinname = (enable_me) ? reg_name : 'bz;

Here is a mini example:

interface mod_if;
wire [7:0] bidir_bus;
logic enable1;
endinterface : mod_if

module one (interface my_if);
assign my_if.bidir_bus = (enable1) ? 8'h11 : 8'hz;
endmodule : one

module two (interface my_if);
assign my_if.bidir_bus = (enable1) ? 8'hz : 8'h22;
endmodule : two

module top();
mod_if my_if();
one m1 (my_if);
two m2 (my_if);

initial begin
my_if.enable1 = 1;
repeat (4)
#1 my_if.enable1 = ~my_if.enable1;
end

initial $monitor(my_if.enable1,, my_if.bidir_bus);
endmodule : top

Kathleen Meade