• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. waveform dump problem using SystemVerilog

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 64
  • Views 18642
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

waveform dump problem using SystemVerilog

archive
archive over 18 years ago

Hi ,
     I am using NcVerilog 5.6 with +sv option to enable SystemVerilog.
I am getting the following error during simulation.

***Current stack trace:
 -->[Don't Know      ] 0         't know>
 -->[Don't Know      ] 5d62b0    ncdbg_exit           + 1bdc
 -->[Don't Know      ] 3eb568    sss_tag_dbend        + 520
 -->[VPI Overhead    ] 136a3c    vpi_tag_ostart       + 191b4
 -->[VPI Overhead    ] 136afc    vpi_tag_ostart       + 19274
 -->[VPI Overhead    ] 1385a8    vpi_tag_ostart       + 1ad20
 -->[VPI Overhead    ] 156f68    vpi_tag_ostart       + 396e0
***Verilog source where error occurs:
   $recordfile(...) (PLI calltf)
        Module: TB_TST
        Instance: TB_TST
        File: ./TB_TST.v
        Line: 422
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.

Can somebody help me.
I am using $recordfile("./filename");
                  $recordvars();
Are these PLI's not supported in SystemVerilog.


Originally posted in cdnusers.org by ravurig
  • Cancel
Parents
  • archive
    archive over 18 years ago

    Hi ravurig,

    I think you may try to use latest IUS583-S003. Because Verilog and SV co-simulation is not stable in old IUS version.

    Regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 18 years ago

    Hi ravurig,

    I think you may try to use latest IUS583-S003. Because Verilog and SV co-simulation is not stable in old IUS version.

    Regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information