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waveform dump problem using SystemVerilog

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Hi ,
     I am using NcVerilog 5.6 with +sv option to enable SystemVerilog.
I am getting the following error during simulation.

***Current stack trace:
 -->[Don't Know      ] 0         't know>
 -->[Don't Know      ] 5d62b0    ncdbg_exit           + 1bdc
 -->[Don't Know      ] 3eb568    sss_tag_dbend        + 520
 -->[VPI Overhead    ] 136a3c    vpi_tag_ostart       + 191b4
 -->[VPI Overhead    ] 136afc    vpi_tag_ostart       + 19274
 -->[VPI Overhead    ] 1385a8    vpi_tag_ostart       + 1ad20
 -->[VPI Overhead    ] 156f68    vpi_tag_ostart       + 396e0
***Verilog source where error occurs:
   $recordfile(...) (PLI calltf)
        Module: TB_TST
        Instance: TB_TST
        File: ./TB_TST.v
        Line: 422
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.

Can somebody help me.
I am using $recordfile("./filename");
                  $recordvars();
Are these PLI's not supported in SystemVerilog.


Originally posted in cdnusers.org by ravurig
Parents

  • I would suggest a couple of things.

    1) As indicated, move to the latest Incisive (NC-Verilog) release which is currently 5.8 available on downloads.cadence.com
    2) File a sourcelink help request or send email to support@cadence.com - most likely support will want a test case which
    reproduces the error.
    3) try switching to shm_open() and shm_dump()
    4) Contact your local Incisive AE who is always more than willing to provide some advice
    5) If you can identify the construct causing the problem, you can always dump "around it".

    I would suspect maybe the dumping of some of the SV TB constructs lagged the implementation a bit and the 5.6 release is
    about 2 years old now. The latest releases have a boatload more field testing these days, are far more stable and offer
    way more features.

    Best regards,

    Jim McG.


    Originally posted in cdnusers.org by Jim McGrath
Reply

  • I would suggest a couple of things.

    1) As indicated, move to the latest Incisive (NC-Verilog) release which is currently 5.8 available on downloads.cadence.com
    2) File a sourcelink help request or send email to support@cadence.com - most likely support will want a test case which
    reproduces the error.
    3) try switching to shm_open() and shm_dump()
    4) Contact your local Incisive AE who is always more than willing to provide some advice
    5) If you can identify the construct causing the problem, you can always dump "around it".

    I would suspect maybe the dumping of some of the SV TB constructs lagged the implementation a bit and the 5.6 release is
    about 2 years old now. The latest releases have a boatload more field testing these days, are far more stable and offer
    way more features.

    Best regards,

    Jim McG.


    Originally posted in cdnusers.org by Jim McGrath
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