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waveform dump problem using SystemVerilog

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Hi ,
     I am using NcVerilog 5.6 with +sv option to enable SystemVerilog.
I am getting the following error during simulation.

***Current stack trace:
 -->[Don't Know      ] 0         't know>
 -->[Don't Know      ] 5d62b0    ncdbg_exit           + 1bdc
 -->[Don't Know      ] 3eb568    sss_tag_dbend        + 520
 -->[VPI Overhead    ] 136a3c    vpi_tag_ostart       + 191b4
 -->[VPI Overhead    ] 136afc    vpi_tag_ostart       + 19274
 -->[VPI Overhead    ] 1385a8    vpi_tag_ostart       + 1ad20
 -->[VPI Overhead    ] 156f68    vpi_tag_ostart       + 396e0
***Verilog source where error occurs:
   $recordfile(...) (PLI calltf)
        Module: TB_TST
        Instance: TB_TST
        File: ./TB_TST.v
        Line: 422
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.

Can somebody help me.
I am using $recordfile("./filename");
                  $recordvars();
Are these PLI's not supported in SystemVerilog.


Originally posted in cdnusers.org by ravurig
Parents

  • Hi All,
    Thank you very much for your suggestions.
    I will try to move to newer version of IUS.

    For time being I have integrated Novas Debussy for waveform dumping using fsdbdumpvars() and fsdbduumpfiles.
    I am able to get my waveform.

    I have used DPI to call C-function in my SV testbench along with my Verilog module.

    I am comparing the simulation speed of SV testbench with Verilog'95 & DPI calling C-function
    and another Verilog testbench with same C-function implemented as behavioral model(Verilog-2001).
    I started the simulation with a view that SV testbench with DPI is going to give me better solution.
    But behavioral model is faster than C-model testbench.

    Case 1:-
    Testbench:- SV
    Verilog module:- '95
    C-model :- Called by SV-DPI.

    Case 2:-
    Testbench:- Verilog'95
    Verilog module:- '95
    C-function as behavioral model:- Verilog 2001(to use its real and other functions).

    I thought Case1 is faster than Case2.

    But my analysis shows Case2 is faster than Case1.

    Can any body help me out.



    Originally posted in cdnusers.org by ravurig
Reply

  • Hi All,
    Thank you very much for your suggestions.
    I will try to move to newer version of IUS.

    For time being I have integrated Novas Debussy for waveform dumping using fsdbdumpvars() and fsdbduumpfiles.
    I am able to get my waveform.

    I have used DPI to call C-function in my SV testbench along with my Verilog module.

    I am comparing the simulation speed of SV testbench with Verilog'95 & DPI calling C-function
    and another Verilog testbench with same C-function implemented as behavioral model(Verilog-2001).
    I started the simulation with a view that SV testbench with DPI is going to give me better solution.
    But behavioral model is faster than C-model testbench.

    Case 1:-
    Testbench:- SV
    Verilog module:- '95
    C-model :- Called by SV-DPI.

    Case 2:-
    Testbench:- Verilog'95
    Verilog module:- '95
    C-function as behavioral model:- Verilog 2001(to use its real and other functions).

    I thought Case1 is faster than Case2.

    But my analysis shows Case2 is faster than Case1.

    Can any body help me out.



    Originally posted in cdnusers.org by ravurig
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