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waveform dump problem using SystemVerilog

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Hi ,
     I am using NcVerilog 5.6 with +sv option to enable SystemVerilog.
I am getting the following error during simulation.

***Current stack trace:
 -->[Don't Know      ] 0         't know>
 -->[Don't Know      ] 5d62b0    ncdbg_exit           + 1bdc
 -->[Don't Know      ] 3eb568    sss_tag_dbend        + 520
 -->[VPI Overhead    ] 136a3c    vpi_tag_ostart       + 191b4
 -->[VPI Overhead    ] 136afc    vpi_tag_ostart       + 19274
 -->[VPI Overhead    ] 1385a8    vpi_tag_ostart       + 1ad20
 -->[VPI Overhead    ] 156f68    vpi_tag_ostart       + 396e0
***Verilog source where error occurs:
   $recordfile(...) (PLI calltf)
        Module: TB_TST
        Instance: TB_TST
        File: ./TB_TST.v
        Line: 422
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.

Can somebody help me.
I am using $recordfile("./filename");
                  $recordvars();
Are these PLI's not supported in SystemVerilog.


Originally posted in cdnusers.org by ravurig
Parents

  • Hi Rav,
      I'm not surprised - SV support is still new and hence may not enjoy all the performance optimizations that good old Verilog 95 has. One suggestion - try using separate ncelab commands - if possible. i.e. in your Case1:

    ******
    Case 1:-
    Testbench:- SV
    Verilog module:- '95
    C-model :- Called by SV-DPI.
    *********

    Compile 95 module using ncvlog -f v95.f
                 ncelab v95_top
           ncvlog -sv31a -f sv.f
           ncelab sv_tb_top v95_top

    Also, since you believe the DPI will give you the boost - do you know how much is the time spent on the C-Verilog/SV intreaction? A profile run should tell you that - unless that PLI is a significant portion you won't see any boost.

    More than this I believe you need to work with your AE to get it better. If you need more help on profiling and general optimization enhancements etc. (not necessariy tied to NC), contact me separately if you wish.

    Good Luck
    Ajeetha, CVC
    www.noveldv.com



    Originally posted in cdnusers.org by ajeetha
Reply

  • Hi Rav,
      I'm not surprised - SV support is still new and hence may not enjoy all the performance optimizations that good old Verilog 95 has. One suggestion - try using separate ncelab commands - if possible. i.e. in your Case1:

    ******
    Case 1:-
    Testbench:- SV
    Verilog module:- '95
    C-model :- Called by SV-DPI.
    *********

    Compile 95 module using ncvlog -f v95.f
                 ncelab v95_top
           ncvlog -sv31a -f sv.f
           ncelab sv_tb_top v95_top

    Also, since you believe the DPI will give you the boost - do you know how much is the time spent on the C-Verilog/SV intreaction? A profile run should tell you that - unless that PLI is a significant portion you won't see any boost.

    More than this I believe you need to work with your AE to get it better. If you need more help on profiling and general optimization enhancements etc. (not necessariy tied to NC), contact me separately if you wish.

    Good Luck
    Ajeetha, CVC
    www.noveldv.com



    Originally posted in cdnusers.org by ajeetha
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