• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. SC and SV co-simulation in IUS?

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 64
  • Views 13965
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SC and SV co-simulation in IUS?

archive
archive over 18 years ago

Hi Cadence,

Is there any SystemC and SystemVerilog in IUS co-simulation example available?
BTW, will IPCM provide such a tutorial to show us how to do this work?

Best regards,
Davy


Originally posted in cdnusers.org by davyzhu
  • Cancel
Parents
  • archive
    archive over 18 years ago

    While CDN shall answer that, what exactly are you looking to use it for? If it is "signal/pin" level interaction bet'n the 2 languages, it should work already as almost all tools support Verilog-SystemC co-simulation. Since SV is on top of Verilog, that basic level interface should work.

    If instead you are looking for a high level - transaction level interface bet'n them, I would imagine that to take a while. Mentor and Synopsys already support that sort of a thing from what I read. One idea will be to use DPI and use struct to pass the information across. It will be great to have class level interaction though LRM doesn't allow this today - unfortunate.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 18 years ago

    While CDN shall answer that, what exactly are you looking to use it for? If it is "signal/pin" level interaction bet'n the 2 languages, it should work already as almost all tools support Verilog-SystemC co-simulation. Since SV is on top of Verilog, that basic level interface should work.

    If instead you are looking for a high level - transaction level interface bet'n them, I would imagine that to take a while. Mentor and Synopsys already support that sort of a thing from what I read. One idea will be to use DPI and use struct to pass the information across. It will be great to have class level interaction though LRM doesn't allow this today - unfortunate.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information