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SC and SV co-simulation in IUS?

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Hi Cadence,

Is there any SystemC and SystemVerilog in IUS co-simulation example available?
BTW, will IPCM provide such a tutorial to show us how to do this work?

Best regards,
Davy


Originally posted in cdnusers.org by davyzhu
Parents

  • Hi Ajeetha,

    Thanks a lot for the information. I heard that IUS have SC/Verilog co-simulation environment, but I haven't used it before.
    Is it on pin layer or transaction layer? Any Cadence engineer can provide such information? Thanks!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
Reply

  • Hi Ajeetha,

    Thanks a lot for the information. I heard that IUS have SC/Verilog co-simulation environment, but I haven't used it before.
    Is it on pin layer or transaction layer? Any Cadence engineer can provide such information? Thanks!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
Children
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