parsing the arguments from command line

Hi.

This is quite easy to do. If you have the Verilog manual, just search for "plusargs".
Here's a small example:
if ( $test$plusargs("verbose") )
$display("a relly verbose message");

Or to get a value from the arguments:

string testname;
TESTNAME_GIVEN : assert ( $value$plusargs("testname+%s", testname) )
else $fatal(1,"No +testname+xyz argument passed to simulator.");
if ( testname == "AddrTest01" ) RunAddrTest01;
else if ( testname == "AddrTest02" ) RunAddrTest02;

Then when calling ncsim:
% ncsim snapshot +testname+AddrTest01 ...

Hope this helps.

Steve.

I don’t know how you will use it with vsim (modelsim) but in ncsim you can use it like shown below,

ncsim –define pkt1=25 –define pkt2=10

This will make the variables pkt1 and pkt2 visible in the code and and inturn you can use it like

int packet1 = ‘pkt1;
int packet2 = ‘pkt2;

Now, use the packet1 with the value 25 and packet2 with value 10.

-Vivek

If $test$plusargs isn't what you need, there's another way to pass arguements  into the simulator.  Any +arguement not recognized by nceverilog or ncsim is passed into the simulator and is available for TCL.  For instance:

ncverilog .... ... ... +test_name+mytestname
or
ncsim ... ... ... +test_name+mytestname

Then this can be extracted via TCL at the NCSim command prompt:

set covTestName "+test_name+"
foreach i $argv {
  if {[string match [format "%s%s" $covTestName "*"] $i]} {
    set my_test_name [string range $i [string length $covTestName ] [string length $i]]
  }
}

puts "Test Name: $my_test_name"