• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. How to probe and view the variable wave in class?

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 64
  • Views 19712
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to probe and view the variable wave in class?

archive
archive over 18 years ago

Hi,

It's happy to know IUS61 is released and have more debug feature.
I have tried the new simvision and found I cannot probe and view the variables wave in class.
Shall I add any particular command to probe it?

Probe command I use now:
database -open -shm -into waves.shm waves -default
probe -create -database waves top -all -depth all -mem -functions -tasks

Best regards,
Davy


Originally posted in cdnusers.org by davyzhu
  • Cancel
Parents
  • archive
    archive over 18 years ago

    Hi Davy,
          As of now tools don't support this. but interestingly Specman (now part of CDN) has been supporting it nicely for half-a-decade atleast! The idea was simple - use a dummy verilog/vhdl stub module/entity and pass on the dynamic values to static world as and when needed. The idea can be related to "callback" method that we demonstrated in our last year SNUG paper with VMM for FIFO. We used a dummy vitural interface named "debug_if" and got similar result.

    Maybe that can help you here for now! I wonder why CDN shall not leverage on Specman's mechanism for this, maybe in pipeline.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 18 years ago

    Hi Davy,
          As of now tools don't support this. but interestingly Specman (now part of CDN) has been supporting it nicely for half-a-decade atleast! The idea was simple - use a dummy verilog/vhdl stub module/entity and pass on the dynamic values to static world as and when needed. The idea can be related to "callback" method that we demonstrated in our last year SNUG paper with VMM for FIFO. We used a dummy vitural interface named "debug_if" and got similar result.

    Maybe that can help you here for now! I wonder why CDN shall not leverage on Specman's mechanism for this, maybe in pipeline.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information