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SV Functional Coverage : Instruction sequence?

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Hi all,

When verify a CPU, I encounter a SV functional coverage problem.
I'd like to check whether there are some back-to-back instructions sequence happened that I am interested in.
Like the instruction sequence:
...
Inst_1 R1, R2
Inst_4 R3, R4
Inst_9 R2, R2
...
But how to define the cover_group? AFAIK, there are control coverage and data coverage, shall I combine them together to get the Instruction sequence coverage?

Another questions that always confused me: I have a transaction generator and monitor(which connected input driver). Shall I get coverage from transaction generator directly or from the monitor connected input driver? IMHO, they are the same. But, what's your opinion?

Any suggestions are welcome!

Best regards,
Davy


Originally posted in cdnusers.org by davyzhu
Parents

  • I wouldn't want to try to do that in a covergroup. Covergroups capture their values on a clock edge. That means that you need to write your own state machines to capture behavior over time. In my example, I wrote a simple one that looked back one instruction fetch. When you get more complicated as in your second example, then you'll end up writing some pretty complex state machines (which themselves would need to be debugged). So I would recommend for those that you use SVA. You can describe a complex sequence very easily in SVA and the simulator will build the state machine for you.

    assert property ( @(posedge clk)
    cmd1 ##1 cmd2 ##1 cmd3 |=> trans1 ##1 trans2 ##1 trans3 );

    This will check for correct behavior ( trans1-2-3 following cmd 1-2-3 ) and the cover report will tell you whether you tested it or not.


    Originally posted in cdnusers.org by TAM
Reply

  • I wouldn't want to try to do that in a covergroup. Covergroups capture their values on a clock edge. That means that you need to write your own state machines to capture behavior over time. In my example, I wrote a simple one that looked back one instruction fetch. When you get more complicated as in your second example, then you'll end up writing some pretty complex state machines (which themselves would need to be debugged). So I would recommend for those that you use SVA. You can describe a complex sequence very easily in SVA and the simulator will build the state machine for you.

    assert property ( @(posedge clk)
    cmd1 ##1 cmd2 ##1 cmd3 |=> trans1 ##1 trans2 ##1 trans3 );

    This will check for correct behavior ( trans1-2-3 following cmd 1-2-3 ) and the cover report will tell you whether you tested it or not.


    Originally posted in cdnusers.org by TAM
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