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"Automatic" keyword supported in NCverilog6.1?

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Hello All, Do the system verilog keyword "automatic" is supported in ncverilog ver 6.1? I tried the following code program automatic test(FIFO_INF.TEST FIFO_INF_U1) // code endprogram The above gave me error, then i tried removing automatic, then the program worked fine. So want to know automatic" keyword is suported or not. Thanks & Regards, Quest Team


Originally posted in cdnusers.org by sundar_80
Parents

  • Hi Sundar.

    A "program" itself can't be "automatic", it just doesn't make sense since a program is like a special version of a module.
    Each program is instantiated in the simulation hierarchy, thus has its own scope and variable instances.
    Automatic is only referring to the program's tasks or functions, because these can be invoked in parallel (i.e. creating multiple threads). In this case automatic tells the simulator to keep separate copies of variables for each invocation of the task/function.

    It sounds like automatic program may not be supported, but you can achieve the exact same effect by declaring all the tasks/functions as automatic inside a normal program block. For example the following two forms should behave identically.
    This would also be clearer to anyone reading the code, since it's then obvious that each task/function has been declared automatic.

    program automatic p1;
    task t1;
    ...
    endtask
    endprogram

    program p2;
    task automatic p2;
    ...
    endtask
    endprogram

    Steve.


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Sundar.

    A "program" itself can't be "automatic", it just doesn't make sense since a program is like a special version of a module.
    Each program is instantiated in the simulation hierarchy, thus has its own scope and variable instances.
    Automatic is only referring to the program's tasks or functions, because these can be invoked in parallel (i.e. creating multiple threads). In this case automatic tells the simulator to keep separate copies of variables for each invocation of the task/function.

    It sounds like automatic program may not be supported, but you can achieve the exact same effect by declaring all the tasks/functions as automatic inside a normal program block. For example the following two forms should behave identically.
    This would also be clearer to anyone reading the code, since it's then obvious that each task/function has been declared automatic.

    program automatic p1;
    task t1;
    ...
    endtask
    endprogram

    program p2;
    task automatic p2;
    ...
    endtask
    endprogram

    Steve.


    Originally posted in cdnusers.org by stephenh
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