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"Automatic" keyword supported in NCverilog6.1?

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Hello All, Do the system verilog keyword "automatic" is supported in ncverilog ver 6.1? I tried the following code program automatic test(FIFO_INF.TEST FIFO_INF_U1) // code endprogram The above gave me error, then i tried removing automatic, then the program worked fine. So want to know automatic" keyword is suported or not. Thanks & Regards, Quest Team


Originally posted in cdnusers.org by sundar_80
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  • Hello Steve,
    Thanks a lot for your reply and from your code i can understand clearly how we can achieve program automatic behavior.
    The basic reason for my query was in "SystemVerilog for Verification" by Chris Spear book, all the example program block contained "program automatic" when i tried to execute the same program in both cadence and modelsim the simulator gave error, so i was under the impression that modelsim and cadence doesn’t support automatic yet. But i have not tried the same example in VCS, anyways thanks a lot for your explanation.

    Sundar


    Originally posted in cdnusers.org by sundar_80
Reply

  • Hello Steve,
    Thanks a lot for your reply and from your code i can understand clearly how we can achieve program automatic behavior.
    The basic reason for my query was in "SystemVerilog for Verification" by Chris Spear book, all the example program block contained "program automatic" when i tried to execute the same program in both cadence and modelsim the simulator gave error, so i was under the impression that modelsim and cadence doesn’t support automatic yet. But i have not tried the same example in VCS, anyways thanks a lot for your explanation.

    Sundar


    Originally posted in cdnusers.org by sundar_80
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