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"Automatic" keyword supported in NCverilog6.1?

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Hello All, Do the system verilog keyword "automatic" is supported in ncverilog ver 6.1? I tried the following code program automatic test(FIFO_INF.TEST FIFO_INF_U1) // code endprogram The above gave me error, then i tried removing automatic, then the program worked fine. So want to know automatic" keyword is suported or not. Thanks & Regards, Quest Team


Originally posted in cdnusers.org by sundar_80
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  • Hi Sundar, Automatic program is valid as per IEEE 1800 standard and I'm sure tools will support them in near future. I also recommend using automatic programs in my [b]SystemVerilog for Verification course [/b] that I deliver in Bangalore (See: www.noveldv.com). It makes life easier with several threads being spawned off with an advanced SV testbench. However as Steve said one can work it around as an interim solution. Here is LRM quote for your reference.

    program_nonansi_header ::= { attribute_instance } program [ lifetime ] program_identifier [ parameter_port_list ] list_of_ports ;
    HTH Ajeetha, CVC www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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  • Hi Sundar, Automatic program is valid as per IEEE 1800 standard and I'm sure tools will support them in near future. I also recommend using automatic programs in my [b]SystemVerilog for Verification course [/b] that I deliver in Bangalore (See: www.noveldv.com). It makes life easier with several threads being spawned off with an advanced SV testbench. However as Steve said one can work it around as an interim solution. Here is LRM quote for your reference.

    program_nonansi_header ::= { attribute_instance } program [ lifetime ] program_identifier [ parameter_port_list ] list_of_ports ;
    HTH Ajeetha, CVC www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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