Task implementation outside module or class?

i think u may have to import the module or package in which the program exists...
import::
this enables u to use all the module properties.... (data types ,functions, tasks.. etc)

Hi,

You can declare tasks (and functions) in a SystemVerilog package. The package contents can then be imported, one-by-one or with a wildcard, into any program or module. This is a cleaner solution than using Verilog `include. e.g.

//simple_package.sv
package simple_package;
   task test();
      $display("This is a test\n");
   endtask // test
endpackage // simple_package

//simple_program.sv
program simple();
   import simple_package::test;

   initial
     begin
        $display("Calling test..");
        test();
     end
endprogram // simple

The command "irun *.sv"  generates the following output:
Calling test..
This is a test

Regards,
Dave