Methodology for attaching Monitors to existing DUT


I'm sharing this code which shows how to connect a verification component,
a monitor in this case, to an existing hierarchy, without modifying ANY of the DUT code.  The attachment of the verification component to the existing dut using an interface is a bit confusing, but is explained here.  The value of this technique is that a verification engineer can instrument a dut without touching any of the original source code.

You can put all the below code in a file called top.sv and use the following to compile:
irun top.sv -linedebug -gui

// This is the interface for the verification component
// Since the verification component is a monitor function
// all signals are input to the verification component
interface verif_if(input a, b, c, d);

endinterface

// -------------------
// This is the hierarchy that the v_monitor will be attached to
module dut(input logic mclk, input logic msig, output logic msigo);

logic aa='b0;   // other potential signals for V1 to attach to

always #17 aa = ~aa;

always @(posedge mclk)
  $display("%m mclk being clocked");

always @(posedge aa)
  $display("%m aa being clocked");

assign msigo = ~msig;

endmodule

// ------------------
module top();
logic tclk='b1;
logic tsig='b0;

dut U1(.mclk(tclk), .msig(tsig), .msigo(tsigo)  );  // .lower(upper)

always #10 tclk = ~tclk;
always #13 tsig = ~tsig;

//always @(posedge tclk)
//  $display("%m tclk being clocked");

endmodule

// ------------------
// The verification module is a seperate top module whose sole
// purpose is to bind verification modules (v_monitor) into
// an existing design (dut) without modifying anything in the
// existing design.

module top_verif(  );

// when using an interface to bind signals into the verification
// component, bind the interface first, then the verif component
// can connect ports and internal signals:

// bind an interface of verif_if called myif to
// instance top.U1 using the following port list
bind top.U1 verif_if myif(mclk, msig, msigo, aa);

// Create an instance called V1 of v_monitor and attach
// it to the instance at top.U1 using the interface
bind top.U1 v_monitor  V1( .vif(myif)  );  // .lower(upper)

endmodule

//----------------
// This module gets attached (uses SV 'bind') to dut
module v_monitor(verif_if vif);  // monitor = all inputs
// In a real monitor insert covergroups, assertions etc here

always @(posedge vif.a)
  $display("V1 a being clocked");

always @(posedge vif.d)
  $display("V1 d being clocked");

endmodule