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Doubt in SV

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Hi Friends! I've doubt in SV regarding enum datatype. pls check the statements below. ncelab: *W,ENUMERR : This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes. My code for this goes here for the reference: typedef enum bit { PASSIVE=0, ACTIVE=1 } active_passive_e; parameter active_passive_e masters_active_passive = {ACTIVE}; defparam master.active_passive = masters_active_passive// My error is in this line //Code ends here Can anyone help me in resolving the issue? What is the error and how shud I solve my problem? Thanks in advance! Regards, Raghavendra


Originally posted in cdnusers.org by raghavendrap
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  • Please note that it is a warning and not an error and therefore your code will still work.

    However, to get rid of the warning, you can either remove the {} surrounding the assignment:

    parameter active_passive_e masters_active_passive = ACTIVE;

    or remove the type definition:

    parameter masters_active_passive = {ACTIVE};

    Tim


    Originally posted in cdnusers.org by tpylant
Reply

  • Please note that it is a warning and not an error and therefore your code will still work.

    However, to get rid of the warning, you can either remove the {} surrounding the assignment:

    parameter active_passive_e masters_active_passive = ACTIVE;

    or remove the type definition:

    parameter masters_active_passive = {ACTIVE};

    Tim


    Originally posted in cdnusers.org by tpylant
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