Intelligent sequence driver

Instead of a sequence driver randomly creating simple sequences like READ and WRITE, I need something with a little more intelligence.

Consider 3 functions, FUNCA, FUNCB, and FUNCC that operate on an address, addr. FUNCA and FUNCC can always randomly occur to any addr. FUNCB can only operate on an addr between the time FUNCA has operated on that addr and FUNCC has operated on the addr. Basically FUNCA to addr=N enables FUNCB to addr=N and FUNC to addr=N disables FUNCB to addr=N.

A sequence like the following can occur:

FUNCC, addr=K 
FUNCA, addr=N  // Enables FUNCB to addr=N
FUNCA, addr=K  // Enables FUNCB to addr=K
FUNCA, addr=N  // N already enabled
FUNCB, addr=N  // FUNCB operating on addr=N 
FUNCB, addr=K  // FUNCB operating on addr=K
FUNCB, addr=N  // FUNCB again operating on addr=N
FUNCC, addr=N  // FUNCB to addr=N disabled
FUNCA, addr=N  // FUNCB to addr=N enabled again
FUNCB, addr=N
FUNCC, addr=K
FUNCC, addr=N

I'm new to SystemVerilog and URM so my questions are the following:

Does the code to keep this state around go in the driver?

Assuming the answer is yes, what are some recommendations on how to create these sequences?

Some ideas I've been given…
Create a list of "legal FUNCB addresses" where:

FUNCA randomly picks an address and adds to the list (if the addr is not in the list already)

FUNCC randomly picks an address and pulls off the list (it wouldn't do anything if the addr was not in the list)

FUNCB counts the length of the list and then randomly chooses a spot in the list to select out the address.

Any other ideas?

Any suggestions for how to code up the idea I've been given?

Thanks,

Ross

Originally posted in cdnusers.org by weberrm