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  3. const logic vector declaration inside a package: IUS6.11...

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const logic vector declaration inside a package: IUS6.11 support

archive
archive over 17 years ago

It seems that a constant logic vector cannot be declared inside a package because it's not supported by IUS6.11

Compiling SIMD package ...
file: simd_pack.v
const logic [log2_regs_num-1:0] FIFO_FA_ADDR      = 0; // FIFO first address address
          |
ncvlog: *W,UNSCON (/IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/simd_pack.v,27|10): The 'const' keyword is not yet implemented in this context.
        package simd.simd_pack:v
                errors: 0, warnings: 1
..done


If the const attribute is removed, the code works in simulation but it's not synthesizable by
dc_shell version    -  Z-2007.03-SP

logic [log2_regs_num-1:0] FIFO_FA_ADDR      = 0; // FIFO first address address


Warning:  /simd_pack.v:50: The 'declaration initial assignment' construct is not supported.  It will be ignored. (VER-104)
Error:  simd_pack.v:50: The construct 'variable declaration in $unit or package' is not supported in synthesis. (VER-700)



BR
Giampiero


Originally posted in cdnusers.org by borgonov69
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  • archive
    archive over 17 years ago

    It is much more common to use an old-style Verilog "parameter" to declare a constant to be used in such a manner.

    localparam [log2_regs_num-1:0] FIFO_FA_ADDR = 'b0;


    Originally posted in cdnusers.org by TAM
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  • archive
    archive over 17 years ago

    It is much more common to use an old-style Verilog "parameter" to declare a constant to be used in such a manner.

    localparam [log2_regs_num-1:0] FIFO_FA_ADDR = 'b0;


    Originally posted in cdnusers.org by TAM
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