Connecting outputs of type "real"?

Hi,
For a system modeling task with sytemverilog, I have various blocks that have outputs of type "real". To match the hardware being modeled (an analog circuit), these outputs need to be connected together. Only one of these blocks would have valid outputs at one time, the others would have a high-impedance ("z") value.
However, there seems to be some fundamental problem with connecting module outputs of type "real" together, since variables cannot have multiple drivers, and "real" data types are variables.

Here is a test case and the result:

module test1;

    real a;
    real b;

    initial
    begin
        a = 0.0;
    end

    test1a t1(.A(a),.B(b));
    test1a t2(.A(a),.B(b));

endmodule

module test1a(A,B);
    input var real A;
    output var real B;

    always @(A)
        B = A;

endmodule

> ncverilog +sv test.v
ncverilog: 06.11-s004: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
file: test.v
        module worklib.test1:v
                errors: 0, warnings: 0
        module worklib.test1a:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        test1a t2(.A(a),.B(b));
                         |
ncelab: *E,MULDRV (./test.v,12|18): Multiple drivers to variable b detected.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.

Does anyone have an idea on how to solve this?

Thanks!
Axel