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  3. errors on SV macros

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errors on SV macros

archive
archive over 17 years ago

Hi guys,
can anybody say how to debug these errors

ncvlog: *E,EOFAMP: EOF found within a text macro actual argument list.

ncvlog: *E,NOTDIR : `include: not a recognized directive or macro.

ncvlog: *E,NOTSTT : expecting a statement.
(For better understanding i've given error code also)
What does these errrors means?
Is this syntax error?--------but i've verified several times there is no syntax mismatch.....
Is this(`include) needs some other thing to be given as reference?


Thanks & Regards,
moneesh


Originally posted in cdnusers.org by sreenagendra_t
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  • archive
    archive over 17 years ago

    It is hard to debug anything like this without the source code. But a wild-guess would be that you have an un-matched quote character in a string or an un-matched parenthesis. The first message makes it look as if it might be in one of your `macro instantiations.

    Try removing code from the bottom of the file, a little bit at a time. Eventually the first syntax error will disappear and the last bit of code you deleted will be the most likely to hold the problem.


    Originally posted in cdnusers.org by TAM
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  • archive
    archive over 17 years ago

    Hi ,
    First of all thank you for giving reply..  
    i am sending the source code also for your clarification..
    If there is any error in source code plz inform me...
    this is testbench for i2s and in this one i took some files to do this ....
                                       
    `include "sips_i2s_if.sv"
     module main_sve_top;                                                                                          
    `include "sips_i2s.sv"
    `include "test_lib.sv"
    reg clock_SCK;
    reg [7:0] data_SD;
    wire transaction_WS;
    sips_i2s_if sips_i2s0(clock_SCK);
    assign sips_i2s0.clock = clock_SCK;
    assign sips_i2s0.data_SD = data_SD;
    assign sips_i2s0.transaction_WS = transaction_WS;
                                                                                                                                 
    initial
       run_test();
    initial
       begin
       $display("clock initial signal");
       clock_SCK =1'b0;
       end
    always
       #50 clock_SCK = ~clock_SCK;
                                                                                                                                 
    endmodule


    Regards
    moneesh


    Originally posted in cdnusers.org by sreenagendra_t
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  • archive
    archive over 17 years ago

    What is in the included files?


    Originally posted in cdnusers.org by shalom
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  • archive
    archive over 17 years ago

    Hi Moneesh,
    Consider sending full code base (with the include files). But even better, do a "grep" for `define in your include files (my wild guess, in your test_lib.sv file) - one of them may have an extra " \ " at the end. - All wild guess as we can't see the full code yet. BTW, we will be releasing a new article on SV macro debug soon on a news letter from CVC - that will show with example a way to debug these using simple text editor commands. Drop me an email if you are interested in looking at it earlier.

    Cheers
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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