Stats

  • Locked Locked
  • Replies 12
  • Subscribers 64
  • Views 20935
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Modularization of SystemVerilog

archive

Hi guys,

I have an question concerning modularization, but I have not found it in one of the following books: "Writing Testbenches using SystemVerilog" and "SystemVerilog for Verification". So, I hope you can help me.

I have written much classes, which are all in ONE file so far, but this is not the target state I wish for this project. The problem is, that for example, one class instantiates another class and I don't know, how to separate the classes.

Is a mechanism available, as C-Header-Files?

I hope you can help me, because several smaller files are much better than one singe huge file.

Thanks for your help!
If the answer should be in one of the itemized books, please sorry, I haven't found it!

Sebastian


Originally posted in cdnusers.org by sebastian

  • Thank you very much for your good advices, tpylant.

    Next question is, where to store the source file for the interfache. I've already found the error messages I get, here in the forum but they don't really help me.

    I will describe, the files I have so far:

    One package which contains all my classes. The classes are all stored in separate files and included in the package. The program containing my testbench, includes the package with the import command. So far, so good.

    I have then a topmodule, which contains the source of the interface and the toplevel module (as described by tpylant above). Furthermore I've written a simple testmodule which "simulates" the real device (actually only tests if interface is working).

    But I don't know how to compile these files and nobody around me can help.

    Because of this fact, I hope, you will help me. So far, my "makefile" looks like the following:

    #! /bin/csh -f

    ncvlog -mess -status -sv pkg.sv env_prog.sv

    ncelab -mess -status -snapshot TEST env_prog

    ncsim -mess -status TEST


    pkg.sv contains the include-commands of the different classes and env_prog contains the program (not the toplevel module).

    Again, thanks for your help!
    Sebastian


    Originally posted in cdnusers.org by sebastian

  • Ok. this problem is solved, I've got same other problems with simulation, but I think the infrastructur itself is ok. To avoid an infinite thread not related with the base topic any more, I will begin a new thread if I need help (and I think I will need help).

    Thanks again @dl_doulos and tpylant for your help!
    Sebastian


    Originally posted in cdnusers.org by sebastian

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.