Modularization of SystemVerilog

Hi Sebastian,

If you have a large number of classes to manage, I would suggest putting them in a SystemVerilog package (this works in a similar way to packages in VHDL).

If you want to use a similar mechanism to C header files, you can always use the Verilog `include "filename" macro.

e.g. in "pkg.sv"

package pkg;

`include "class1.sv"
`include "class2.sv"
...

endpackge

To use package in module (usually in another file):

module top;

import pkg::*; //make all package items visible here

...

endmodule


----------------------------

Hope that helps.
Regards,
Dave

Dave answered the question about partitioning up the classes into smaller packages. That is definitely the way to go and then you can "import" the packages you need into the modules. Of course you will need to make sure that you pass the package files to the compiler before the modules that need to import them. I think you may have also asked about how to call a class that hasn't been defined in another class. The way to do that is to use typedef as in this example: typedef class future_c; class current_c; future_c f; ... endclass class future_c; ... endclass The class future_c can be in the same file as current_c or in another file as long as both classes are visible to the compiler during the same compilation run. Tim

Hi,

thanks for the fast replies. I have tried so, but something seems to go wrong at compilation: the classes I exported to packages, are unknwon.

The source code is:

import pkg::* //make all package items visible here

program testprogram;

parameter MODE_FIX = 0;

// and so on

endprogram

I try to compile with the following command:

ncvlog -mess -status -sv testprogram.sv

I have also tried the following:

ncvlog -mess -status -sv testproam.sv pkg.sv

I hope, the classes need not to be declared within the key word "program ..."

Thanks for your help, alone I would be in a fix (is this correct English? :) )

Sebastian

You need to compile the pkg.sv file first, i.e. "ncvlog -mess -status -sv pkg.sv testproam.sv".


Since you are importing "pkg::*", I assume that the package name is "pkg", i.e. "package pkg; ... endpackage".


The import statement does not have to be within the program block, however by putting it outside, all of the package declarations are visible to any modules/programs/etc. that follow the import statement. I personally do not recommend that because it follows poor coding guidelines and can cause unforseen problems. It is better to import the package into each module where you want to use it. However, if you want to ignore that advice for a legitimate reason, then you might as well put the import statemetn at the end of your package file, i.e. "package pkg; ... endpackage import pkg::*;"

Tim

Hi,

the next problem has occured and I hope you will help me again. :)

I have written a source code like this:

program test();

// definition of class class_1
........
// definition of class class_n

class_1 one;
class_n n;

initial begin
one = new;
n = new;

// do something

endprogram : test


It worked so far. To be able to put the classes into separate files, I have tried to put

program test();

just before "class_1 one;

Now, the compiler tells me: Unrecognized declaration 'class_1' etc.

Chris Spear writes on his book:"SystemVerilog for verification" on page 69 (section 4.4):
Zou can define a class in SystemVerilog in a program, module, package, or outside of any these. Classes can be used in programs and modules."

So, what am I doing wrong???
I'm not able to find any error.

Thanks for your patience!
Sebastian

To make it worse, class_n instantiates an object of class_1. I hope, this will not be an additional problem!

Sebastian

I think this is what you are looking for: package pkg; typedef class class_n; class class_1; class_n n; function new(); n = new(); endfunction endclass class class_n; endclass endpackage : pkg program test; import pkg::*; class_1 one; class_n n; initial begin one = new(); n = new(); end endprogram : test I also want to note that although the LRM states that you can put class definitions "outside of any of these", IUS only supports classes defined in program, module, or package. This should never be a problem since a package accomplishes the same thing but in a more reusable and structured format (see my previous post about using the import statement). Tim

Thanks!

The forward declaration was the critical point, now it works!

Sebastian

And yet another question, I'm sorry for this, but I'm unexperienced in Verilog, SystemVerilog AND verification in general, so this is very hard. I've read books about verification in general, without any specific language and books concerning only Verilog and SystemVerilog, but the questions are appearing during programming.

So here's my question:

I've separated the classes in single files and packed them together in one class (with help of the keywords typedef, `include and of course with the help of you all here.

My next task is to connect to "top level classes" (as described in Spear: page 212 - 213 with interfaces, because at the moment, no DUV is available.

Now, I'm very unsure and don't know how to realise this task.

Shall I implement two program blocks inside a module which both gets the same interface? For example:

module top;

interface if_inst;

program1 (interface if_inst.if_master);

Environment env1;
......

endprogram

program2 (interface if_inst.if_slave);

Environment env2;

endprogram

endmodule


Thanks for your great help, without this I wouldn't be able to get ahead.
Have a nice weekend!
Sebastian

The program blocks are instantiated but not defined within the top level module. I would recommend that each test be in its own file just like any other module.

program test1(interface di);
  ...
endprogram

program test2(interface di)
  ...
endprogram

module top();
  dut_interface di();
  dut_mod dut();
  test1 test(di);
endmodule

I would also recommend looking at the documentation and examples that are provided with the new OVM (Open Verification Methodology) release. The OVM library does a lot of the work of building the infrastructure for you and automates the building of the environment. The documentation will walk you through how to use it and the examples give you working code to start with.

You can get the OVM download from http://www.ovmworld.org and also see more discussion at http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/5960/view/topic/Default.aspx.

Tim