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Modularization of SystemVerilog

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Hi guys,

I have an question concerning modularization, but I have not found it in one of the following books: "Writing Testbenches using SystemVerilog" and "SystemVerilog for Verification". So, I hope you can help me.

I have written much classes, which are all in ONE file so far, but this is not the target state I wish for this project. The problem is, that for example, one class instantiates another class and I don't know, how to separate the classes.

Is a mechanism available, as C-Header-Files?

I hope you can help me, because several smaller files are much better than one singe huge file.

Thanks for your help!
If the answer should be in one of the itemized books, please sorry, I haven't found it!

Sebastian


Originally posted in cdnusers.org by sebastian
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  • And yet another question, I'm sorry for this, but I'm unexperienced in Verilog, SystemVerilog AND verification in general, so this is very hard. I've read books about verification in general, without any specific language and books concerning only Verilog and SystemVerilog, but the questions are appearing during programming.

    So here's my question:

    I've separated the classes in single files and packed them together in one class (with help of the keywords typedef, `include and of course with the help of you all here.

    My next task is to connect to "top level classes" (as described in Spear: page 212 - 213 with interfaces, because at the moment, no DUV is available.

    Now, I'm very unsure and don't know how to realise this task.

    Shall I implement two program blocks inside a module which both gets the same interface? For example:

    module top;

    interface if_inst;

    program1 (interface if_inst.if_master);

    Environment env1;
    ......

    endprogram

    program2 (interface if_inst.if_slave);

    Environment env2;

    endprogram

    endmodule


    Thanks for your great help, without this I wouldn't be able to get ahead.
    Have a nice weekend!
    Sebastian


    Originally posted in cdnusers.org by sebastian
Reply

  • And yet another question, I'm sorry for this, but I'm unexperienced in Verilog, SystemVerilog AND verification in general, so this is very hard. I've read books about verification in general, without any specific language and books concerning only Verilog and SystemVerilog, but the questions are appearing during programming.

    So here's my question:

    I've separated the classes in single files and packed them together in one class (with help of the keywords typedef, `include and of course with the help of you all here.

    My next task is to connect to "top level classes" (as described in Spear: page 212 - 213 with interfaces, because at the moment, no DUV is available.

    Now, I'm very unsure and don't know how to realise this task.

    Shall I implement two program blocks inside a module which both gets the same interface? For example:

    module top;

    interface if_inst;

    program1 (interface if_inst.if_master);

    Environment env1;
    ......

    endprogram

    program2 (interface if_inst.if_slave);

    Environment env2;

    endprogram

    endmodule


    Thanks for your great help, without this I wouldn't be able to get ahead.
    Have a nice weekend!
    Sebastian


    Originally posted in cdnusers.org by sebastian
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