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Modularization of SystemVerilog

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Hi guys,

I have an question concerning modularization, but I have not found it in one of the following books: "Writing Testbenches using SystemVerilog" and "SystemVerilog for Verification". So, I hope you can help me.

I have written much classes, which are all in ONE file so far, but this is not the target state I wish for this project. The problem is, that for example, one class instantiates another class and I don't know, how to separate the classes.

Is a mechanism available, as C-Header-Files?

I hope you can help me, because several smaller files are much better than one singe huge file.

Thanks for your help!
If the answer should be in one of the itemized books, please sorry, I haven't found it!

Sebastian


Originally posted in cdnusers.org by sebastian
Parents

  • Hi,

    the next problem has occured and I hope you will help me again. :)

    I have written a source code like this:

    program test();

    // definition of class class_1
    ........
    // definition of class class_n

    class_1 one;
    class_n n;

    initial begin
    one = new;
    n = new;

    // do something

    endprogram : test


    It worked so far. To be able to put the classes into separate files, I have tried to put

    program test();

    just before "class_1 one;

    Now, the compiler tells me: Unrecognized declaration 'class_1' etc.

    Chris Spear writes on his book:"SystemVerilog for verification" on page 69 (section 4.4):
    Zou can define a class in SystemVerilog in a program, module, package, or outside of any these. Classes can be used in programs and modules."

    So, what am I doing wrong???
    I'm not able to find any error.

    Thanks for your patience!
    Sebastian


    Originally posted in cdnusers.org by sebastian
Reply

  • Hi,

    the next problem has occured and I hope you will help me again. :)

    I have written a source code like this:

    program test();

    // definition of class class_1
    ........
    // definition of class class_n

    class_1 one;
    class_n n;

    initial begin
    one = new;
    n = new;

    // do something

    endprogram : test


    It worked so far. To be able to put the classes into separate files, I have tried to put

    program test();

    just before "class_1 one;

    Now, the compiler tells me: Unrecognized declaration 'class_1' etc.

    Chris Spear writes on his book:"SystemVerilog for verification" on page 69 (section 4.4):
    Zou can define a class in SystemVerilog in a program, module, package, or outside of any these. Classes can be used in programs and modules."

    So, what am I doing wrong???
    I'm not able to find any error.

    Thanks for your patience!
    Sebastian


    Originally posted in cdnusers.org by sebastian
Children
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