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Modularization of SystemVerilog

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Hi guys,

I have an question concerning modularization, but I have not found it in one of the following books: "Writing Testbenches using SystemVerilog" and "SystemVerilog for Verification". So, I hope you can help me.

I have written much classes, which are all in ONE file so far, but this is not the target state I wish for this project. The problem is, that for example, one class instantiates another class and I don't know, how to separate the classes.

Is a mechanism available, as C-Header-Files?

I hope you can help me, because several smaller files are much better than one singe huge file.

Thanks for your help!
If the answer should be in one of the itemized books, please sorry, I haven't found it!

Sebastian


Originally posted in cdnusers.org by sebastian
Parents

  • The program blocks are instantiated but not defined within the top level module. I would recommend that each test be in its own file just like any other module.

    program test1(interface di);
      ...
    endprogram

    program test2(interface di)
      ...
    endprogram

    module top();
      dut_interface di();
      dut_mod dut();
      test1 test(di);
    endmodule
    I would also recommend looking at the documentation and examples that are provided with the new OVM (Open Verification Methodology) release. The OVM library does a lot of the work of building the infrastructure for you and automates the building of the environment. The documentation will walk you through how to use it and the examples give you working code to start with.

    You can get the OVM download from http://www.ovmworld.org and also see more discussion at http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/5960/view/topic/Default.aspx.

    Tim


    Originally posted in cdnusers.org by tpylant
Reply

  • The program blocks are instantiated but not defined within the top level module. I would recommend that each test be in its own file just like any other module.

    program test1(interface di);
      ...
    endprogram

    program test2(interface di)
      ...
    endprogram

    module top();
      dut_interface di();
      dut_mod dut();
      test1 test(di);
    endmodule
    I would also recommend looking at the documentation and examples that are provided with the new OVM (Open Verification Methodology) release. The OVM library does a lot of the work of building the infrastructure for you and automates the building of the environment. The documentation will walk you through how to use it and the examples give you working code to start with.

    You can get the OVM download from http://www.ovmworld.org and also see more discussion at http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/5960/view/topic/Default.aspx.

    Tim


    Originally posted in cdnusers.org by tpylant
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