Stats

  • Locked Locked
  • Replies 4
  • Subscribers 64
  • Views 13892
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SV Implementation of dynamic array of memory?

archive

Hi Friends,
     I want to implement a buffer where I can insert & delete an element flexibly. What I mean to say is something similar to keyed list in specman, I want to implement in SV CB methodology using URM.
   I tried using dynamic memory but I failed creating "new address"(suppose address as my key) for every element I want to add at every other instant of time.

rand int buffer[];
int j = 0;

task ins_element(input [31:0] data);
buffer[j] = new;
buffer[j] = data;
j++;
endtask

Note:  I don't want STACK or FIFO type of implementation here where the array length of memory is static

Here the error is "The function new cannot be used to creat an object to assign to this variable"
Can anyone help me in this regards so as to suggest me how to proceed?

Thanks in advance,
Jalli


Originally posted in cdnusers.org by jaally

  • hi Jalli,

    The functionality you want is being implement in below example. I hope it solves your problem.

    Example
    module temp();

    int buffer[];
    int j = 0;

    task ins_element(input [31:0]data);
    buffer = new[j+1](buffer);
    buffer[j] = data;
    j++;
    endtask

    initial
    begin
    ins_element(32);
    ins_element(30);
    ins_element(35);
    ins_element(4);

    #10;
    for (int i = 0 ; i < buffer.size(); i++)
    begin

    $display ( "array values %0d = %0d", i, buffer[i]);
    end
    $finish;
    end

    endmodule

    Result:

    #Loading sv_std.std
    # Loading work.temp(fast)
    # run -all
    # array values 0 = 32
    # array values 1 = 30
    # array values 2 = 35
    # array values 3 = 4
    # ** Note: $finish : temp.sv(25)


    To delete from buffer can use below task.
    task del_element();
    buffer = new[j-1](buffer);

    j--;
    endtask

    I hope it cover your requirement.


    Originally posted in cdnusers.org by divyeshg

  • Hi Divyesh,

    Thanks a lot. It did work but I wanna know which book you referred for this so that I can follow the same for SV usage.

    Thanks again,
    Regards,
    Jalli


    Originally posted in cdnusers.org by jaally

  • Hi Jalli,

    I am referring "SystemVerilog 3.1a Language Reference Manual".


    Originally posted in cdnusers.org by divyeshg

  • Hi Divyesh.

    The Accellera 3.1a spec is quite old now, and is not an official standard.
    The best spec to reference is the IEEE1800, which is the official SystemVerilog spec.
    You should be able to view it here:
    http://ieeexplore.ieee.org/servlet/opac?punumber=4410438

    Regards,
    Steve


    Originally posted in cdnusers.org by stephenh

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.