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struck in arithmetic

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Hi Friends,
 I couldn't debug this error  while I"m working on UVC using SVCB. Can anyone help me in this regards?

   =>   j = j + 1;
    ncvlog *E BADCON:  Illegal Concatenation Syntax
Below is the rough sketch of the code:

     class my_class extends urm_bfm;
           .........
           int j;
           task my_task;
                  .........
                  j = j + 1;
            endtask
           ...........
     endclass
      
Thanks in advance,
Regards,
Jalli


Originally posted in cdnusers.org by jaally
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  • Hi Jalli. I'm glad it solved your problem :-)

    I think the compiler did a reasonable job of pointing you to the problem, because it reported "illegal concatenation syntax" on the first line after the opening bracket.
    In Verilog (and SystemVerilog), the curly brackets are used to define concatenation, e.g:
    assign some_2_bit_sig = { 1'b1, a_1_bit_sig };

    So the compiler saw an opening bracket, followed by some procedural code which did not fit the expected pattern.
    It's often the case for compilers (in any language) to flag an error on some line after the actual problem, simply because of the way compilers have to work.

    Hope this helps.


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Jalli. I'm glad it solved your problem :-)

    I think the compiler did a reasonable job of pointing you to the problem, because it reported "illegal concatenation syntax" on the first line after the opening bracket.
    In Verilog (and SystemVerilog), the curly brackets are used to define concatenation, e.g:
    assign some_2_bit_sig = { 1'b1, a_1_bit_sig };

    So the compiler saw an opening bracket, followed by some procedural code which did not fit the expected pattern.
    It's often the case for compilers (in any language) to flag an error on some line after the actual problem, simply because of the way compilers have to work.

    Hope this helps.


    Originally posted in cdnusers.org by stephenh
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