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$Signal_force

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Hi everyone,
I am trying to use $signal_force but i am running into some problems. I am not sure how to use this command to force a signal not directly to a value but actually to another signal.
to elaborate on this, i give an example.
within my test bench i have a logic signal of size 32 bits called data1 and its value gets updated on each clock cycle. i would like to force a std_logic_vector of 32 bits to data1. but i always get a erro. it seems like i am not allowed to pass a signal as the specified value within signal_force.

$signal_force ("/../../../../input_data", "data1",0,3, ,1)
$signal_force(,,other_options..)
this is where i get the error.
i would like to know if this is legal to do.


Originally posted in cdnusers.org by ROOZ

  • I believe the "$signal_force" command is modelsim specific. If you are using modelsim, please consult the modelsim documentation. Cadence Incisive supports a similar command called, "$nc_force()". This is documented in the
    "NC Verilog Simulator Help Manual" in Chapter 19 - Applications.

    Regards,

    Jim McGrath


    Originally posted in cdnusers.org by Jim McGrath

  • I did check the questasim documentation but it didn't have an answer to my question. that's the reason for posting the question here. but thanks for your response


    Originally posted in cdnusers.org by ROOZ

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