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Implicit events in system verilog

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In specman, we can create events in both explicit and implicit way. Implicit creation event xyz is {@req;[2];@gnt}@clk_r; The same can be created explicitly by event xyz; tcm()@clk_r { while TRUE { @req; wait[2]; @gnt; emit xyz; }; } In system verilog, the events can be created explicitly. Is there a way I can create events implicitly in system verilog. Thanks


Originally posted in cdnusers.org by pandyk

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