In what aspects is verification different from design?

Akiva asked:

"I want to pose a simple question: In what ways is Verification different from Design? (ways which might affect planning)"

I'd like to toss out a few ideas :

Although both Design and Verification engineers start with a functional spec and proceed towards a common goal of releasing as functionally correct a design as possible on schedule, the activities and focus of each differs considerably.

Design engineers design and implement the design given constraints of time, resources, process technology etc.  They need to be concerned with the application environment to some degree but are primarily concerned with the world inside the design.

Verification engineers design and implement a model of the application environment in which the design is intended to operate, within constraints of time, resources, capabilities of verification methodology and tools etc.  They need to be aware of implementation aspects of the design but are primarily concerned with the world around the design. 

For example, in the case of a digital camera design the application environment would include a model of the user (sets modes, takes pictures etc.), other entities that connect to the camera (printers, PC, memory card, battery etc.), the infinite set of images that the camera is required to capture and so on.  In addition, the verifier must design and implement a set of checkers to verify that the design responds correctly and some means to measure how well each feature was exercised (aka coverage). 

With that background and considering planning to be the process in which a list of features to verify is built, the approach (formal/simulation/acceleration etc.) to verify features is prescribed and the environment(s) are specified, in the planning process both designers and verifiers are required to work with the set of design features, but the verifier is concerned with using the feature descriptions to determine the verification approach, specify the requirements for the verification environments and devise coverage measurements to ensure that each feature is adequately exercised.

An additional thought relates to tracking the progress of the development process.  Since the % of specified features that have been verified can be considered a reasonable measure of progress, the burden of tracking progress of the development process often falls on the verification engineer.  This requires the planning process to be approached in a way that the information captured can be used to provide a credible measure of progress that addresses both completeness (have all features been implemented?) and correctness (have they been implemented correctly?).

I hope these ideas help move the discussion forward and I look forward to participating further.

Regards,
Dean

Akiva asked:

"I want to pose a simple question: In what ways is Verification different from Design? (ways which might affect planning)"

I'd like to toss out a few ideas :

Although both Design and Verification engineers start with a functional spec and proceed towards a common goal of releasing as functionally correct a design as possible on schedule, the activities and focus of each differs considerably.

Design engineers design and implement the design given constraints of time, resources, process technology etc.  They need to be concerned with the application environment to some degree but are primarily concerned with the world inside the design.

Verification engineers design and implement a model of the application environment in which the design is intended to operate, within constraints of time, resources, capabilities of verification methodology and tools etc.  They need to be aware of implementation aspects of the design but are primarily concerned with the world around the design. 

For example, in the case of a digital camera design the application environment would include a model of the user (sets modes, takes pictures etc.), other entities that connect to the camera (printers, PC, memory card, battery etc.), the infinite set of images that the camera is required to capture and so on.  In addition, the verifier must design and implement a set of checkers to verify that the design responds correctly and some means to measure how well each feature was exercised (aka coverage). 

With that background and considering planning to be the process in which a list of features to verify is built, the approach (formal/simulation/acceleration etc.) to verify features is prescribed and the environment(s) are specified, in the planning process both designers and verifiers are required to work with the set of design features, but the verifier is concerned with using the feature descriptions to determine the verification approach, specify the requirements for the verification environments and devise coverage measurements to ensure that each feature is adequately exercised.

An additional thought relates to tracking the progress of the development process.  Since the % of specified features that have been verified can be considered a reasonable measure of progress, the burden of tracking progress of the development process often falls on the verification engineer.  This requires the planning process to be approached in a way that the information captured can be used to provide a credible measure of progress that addresses both completeness (have all features been implemented?) and correctness (have they been implemented correctly?).

I hope these ideas help move the discussion forward and I look forward to participating further.

Regards,
Dean