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TB Simplification

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Hello All, In the process of verification, we develop many TestBenches those are useful for the module-level verification only. Once the module is verified, a new TB is developed for another module. Is there any alternative way to this approach, wherein we can reduce the time spent on the development of TB for each and every module? Is there any reusable approach for this? Any ideas or suggestions are welcome. -Vivek


Originally posted in cdnusers.org by prasad_vc
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  • Hi Vivek.

    That's a very good question! Fortunately the URM (Universal Reuse Methodology) is designed specifically for this problem.
    Whether you choose to code in e, SystemVerilog or SustemC, the methodology guides you through building a reusable testbench based on modular components. These guidelines have been developed through very close cooperation between Cadence and many customers over several years, so they really work.

    The idea is to build everything in component form (e.g. bus interface components, sequence generators, protocol layering).
    Each component is then used in a "testbench" that itself is designed to be plugged into a higher level testbench if needed.

    You should take a look at http://myipcm.cadence.com/ for the online books that describe the methodology.
    Also, get in touch with your local Cadence AE who can help you plan you verification.


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Vivek.

    That's a very good question! Fortunately the URM (Universal Reuse Methodology) is designed specifically for this problem.
    Whether you choose to code in e, SystemVerilog or SustemC, the methodology guides you through building a reusable testbench based on modular components. These guidelines have been developed through very close cooperation between Cadence and many customers over several years, so they really work.

    The idea is to build everything in component form (e.g. bus interface components, sequence generators, protocol layering).
    Each component is then used in a "testbench" that itself is designed to be plugged into a higher level testbench if needed.

    You should take a look at http://myipcm.cadence.com/ for the online books that describe the methodology.
    Also, get in touch with your local Cadence AE who can help you plan you verification.


    Originally posted in cdnusers.org by stephenh
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