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howto? triggering event off 1 bit of uint simple_port

archive

I have a simple port of uint(bits:NUM_BITS).  I want to trigger
an event based on a single bit of this port, e.g.

event foo is rise( my_port$[0:0] )@sim;

Is this possible?

Here is a complete example:
#### top.v ####
module top();
   
    reg [32:0] my_signal;
   
    initial begin
        $display("TOP.V: BEGIN test");
        my_signal =  0;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal = -1;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal =  0;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal = -1;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal =  0;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal = -1;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal =  0;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        my_signal = -1;
        $displayb("TOP.V: my_signal = '%d'",my_signal);
        #10
        $display("TOP.V: END test");
    end
   
endmodule

#### test.e ####
<'

unit foo_u {
    my_port : simple_port of uint(bits:32) is instance;
    keep bind(my_port,external);
    keep my_port.hdl_path() == "~/top/my_signal";
   
    event bit0_posedge_e is rise( my_port$[0:0] )@sim;
   
    on bit0_posedge_e {
        out( "Event 'bit0_posedge_e' seen");
    };
   
};
 
extend sys {
    foo : foo_u is instance;
    run() is also{
        out("hello!!");
    };
};


'>
#### makefile ####

.PHONY: all
all: specrun

specman.v: test.e
    @echo "## Creating specman.v"
    specman -c  "load test.e; write stubs -vcs"

vcs_specman: top.v specman.v
    sn_compile.sh -sim vcs                  \
        -sim_flags "top.v specman.v -debug -l runsim.log "

.PHONY: specrun
specrun: specman.v test.e top.v vcs_specman
    @echo ""
    specrun -p "load test.e" ./vcs_specman -ucli

clean:
    -rm -rf vcs_specman specman.v csrc .vcsmx_rebuild specman.elog runsim.log \
        vcs_specman.daidir ag_command.log jspecview.log simv *log test.esv test \
        ucli.key vcs.key vcs_test vcs_test.daidir
   

When I run, I get:
## Creating specman.v
specman -c  "load test.e; write stubs -vcs"
Welcome to Specman Elite (6.1)  -  Linked on Sun Apr  1 10:15:44 2007

Protected by U.S. Patents 6,920,583; 6,918,076; 6,907,599; 6,687,662;
6,684,359; 6,675,138; 6,530,054; 6,519,727; 6,502,232; 6,499,132; 6,487,704;
6,347,388; 6,219,809; 6,182,258; 6,141,630; Other Patents Pending.

Checking license ... OK
Loading test.e ...
read...parse...update...patch...h code...code...
   *** Error: Unrecognized exp
    [Unrecognized expression '0:0']
                at line 10 in test.e
    event bit0_posedge_e is rise( my_port$[0:0] )@sim;
                                           ^^^




Load failed - restored
/nfs/site/eda/group/SYSNAME/lrb/verisity/specman/6.1/components/sn/linux/specman.esv
make: *** [specman.v] Error 255

Is this possible?  How would I do this?


Originally posted in cdnusers.org by LDiracDelta
Parents

  • I coded up two little examples:

    <'

    unit test_1_u {
    my_val : uint(bits:32);
    my_p : simple_port of uint(bits:32) is instance;
    keep bind(my_p,external);
    keep my_p.hdl_path()=="my_signal";
    event ch_p_e is change(my_p$) @sim exec {my_val=my_p$};
    event bit_0_e is rise(my_val[0:0]) @ch_p_e;
    };

    unit test_2_u {
    my_p : simple_port of uint(bits:32) is instance;
    keep bind(my_p,external);
    keep my_p.hdl_path()=="my_signal";
    keep my_p.declared_range()=="[0:0]";

    event bit_0_e is rise(my_p$) @sim;
    };



    '>


    Hope this helps,
    Hilmar


    Originally posted in cdnusers.org by Hilmar
Reply

  • I coded up two little examples:

    <'

    unit test_1_u {
    my_val : uint(bits:32);
    my_p : simple_port of uint(bits:32) is instance;
    keep bind(my_p,external);
    keep my_p.hdl_path()=="my_signal";
    event ch_p_e is change(my_p$) @sim exec {my_val=my_p$};
    event bit_0_e is rise(my_val[0:0]) @ch_p_e;
    };

    unit test_2_u {
    my_p : simple_port of uint(bits:32) is instance;
    keep bind(my_p,external);
    keep my_p.hdl_path()=="my_signal";
    keep my_p.declared_range()=="[0:0]";

    event bit_0_e is rise(my_p$) @sim;
    };



    '>


    Hope this helps,
    Hilmar


    Originally posted in cdnusers.org by Hilmar
Children
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