Stats

Locked Locked
Replies 17
Subscribers 64
Views 18308
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

sequences

hi dudes, can anybody help me. my question is, while doing eVC with eRM methodology we r using sequences for stimulus generation and If we r not using eRM methodology then how can we generate stimulus? can anybody give me brief about it.

Originally posted in cdnusers.org by vlsi_dude

Parents

archive over 18 years ago

Do you have specman_reference instatiated in VHDL code e.g. in VHDL testbench?

Originally posted in cdnusers.org by pjigar
Cancel
Vote Up 0 Vote Down

Cancel

Reply

archive over 18 years ago

Do you have specman_reference instatiated in VHDL code e.g. in VHDL testbench?

Originally posted in cdnusers.org by pjigar
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.