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accessing hdl signals in mixed language env

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Hi, I have used define statements to acesses dut signals. Worked fine when the entire dut hierarchy was vhdl. Now with vhdl-verilog(netlist) specman says 'signal not found'.(it does exist) Eg:- define sig_a "~/c/b/a";-- where c--vhdl --and all heirachy at b and below is verilog. I am using sig_a inside a TCM which is a member of tb_env. Any solutions. Thanks, pr


Originally posted in cdnusers.org by rprashant
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  • Sorry the forum mashed my code example!
    Trying again:

    // declare the port
    sig_a : inout simple_port of bit is instance;
    // sig_a is a simulator signal rather than an e-to-e port
    keep bind(sig_a, external);
    // bind the HDL signal name.
    // Can be done in top-level config file for best re-use
    keep sig_a.hdl_path() == "~/c/b/a";


    Originally posted in cdnusers.org by stephenh
Reply

  • Sorry the forum mashed my code example!
    Trying again:

    // declare the port
    sig_a : inout simple_port of bit is instance;
    // sig_a is a simulator signal rather than an e-to-e port
    keep bind(sig_a, external);
    // bind the HDL signal name.
    // Can be done in top-level config file for best re-use
    keep sig_a.hdl_path() == "~/c/b/a";


    Originally posted in cdnusers.org by stephenh
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