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accessing hdl signals in mixed language env

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Hi, I have used define statements to acesses dut signals. Worked fine when the entire dut hierarchy was vhdl. Now with vhdl-verilog(netlist) specman says 'signal not found'.(it does exist) Eg:- define sig_a "~/c/b/a";-- where c--vhdl --and all heirachy at b and below is verilog. I am using sig_a inside a TCM which is a member of tb_env. Any solutions. Thanks, pr


Originally posted in cdnusers.org by rprashant
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  • in mixed HDL environments it is important to make sure SPMN knows which interface adapter to use to access specific signals.
    if you only have one HDL language then there is only one interface adapter. In mixed environments SPMN will use several interface adapters. you should read the documentation regarding the agent() attribute of units [e Language Reference - 5.3 Predefined Attributes and Methods for Any Unit]. this will define the correct agent to use and will ensure that the right signal is found.


    Originally posted in cdnusers.org by hannes
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  • in mixed HDL environments it is important to make sure SPMN knows which interface adapter to use to access specific signals.
    if you only have one HDL language then there is only one interface adapter. In mixed environments SPMN will use several interface adapters. you should read the documentation regarding the agent() attribute of units [e Language Reference - 5.3 Predefined Attributes and Methods for Any Unit]. this will define the correct agent to use and will ensure that the right signal is found.


    Originally posted in cdnusers.org by hannes
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