Interfacing Specman with NCSIM

If you're using a recent version of Specman and IUS, then the irun command is your friend.
irun will compile your Verilog, VHDL, e, SystemC etc in one easy step - no need for your own scripting.

Also, there is no need to use the "call sn" command any more.
Now, at the ncsim prompt you can just do "sn " - there is no need to switch back and forward manually.
For example, your ncsim.tcl script can mix specman and ius commands:

sn load test.e
sn test
sn trace sequence transactions
probe -create -shm -all -depth all
run 100 ns

Thanks Steve,

I will try this.

Hello Steve,

I have tried these commands.
But ncsim giving the error that "sn" is not an command in ncsim.
I m using specman 5.0 and IUS 5.5.

I used "call sn" command also in that it's getting hanged at design browser of ncsim.
If i m using call sn then sn test, both of these commands are running at ncsim prompt but i need that sn test will run on specman prompt.

Please help me..

Thanks

OK, the problem is that you're using fairly old versions of IUS and Specman.
If you can upgrade to Specman 6.11 and IUS 6.11 you will find that they play very nicely together.
In fact the integration is much better even from Specman 5.1 and IUS 5.7, but if you're upgrading then it's best to jump to the latest versions...
For example the Specman buttons are now integrated into SimVision GUI, and the SimVision Design Browser also shows the "sys" hierarchy next to the HDL. You can trace sequences direct to the waveform window ("sn trace sequence transactions" command).

If you really cannot upgrade, I think you should be ok to do things like this from the NCSim TCL script:
call sn {load test}
call sn {test -seed random}
run

Hi

I am using "irun" command for mixed hdl simulation (i.e. verilog testbench and vhdl dut) with e env.

I am facing problem that i am not able to see the values of internal module signals in the waveform.

My verilog testbench is top.v and vhdl top(DUT) is dut.vhd.

Command that i am using is:

"irun top.e top.v dut.vhd -top dut -gui"

Thanks

Hi vlsi_dude. This would probably have been a good point to start a new topic.

By default, ncelab and irun do not instrument the snapshot with access to signals in the design.
This is done for performance reasons - less visibility makes for faster simulations.
You can use the "-access +r" option to ncelab or irun to add read access to signals, allowing you to trace the waveforms.
Alternatively use "-access +rc" to enable connectivity tracing as well, so you can trace drivers / loads in SimVision.

Finally, you could use an access control file "-afile access.cfg" to list all the blocks where you need visibility - this lets you trade performance and visibility into the design by selecting only the areas you need to see into.

Thanks Steve,

Now I am able to access the internal signal.