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error in eVC with VHDL DUT testing

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Hi friends,

   I've written an I2S eVC and trying to test with a I2S DUT written in VHDL including the testbench.

I got this error on linux platform when using NCSIM & specman. can anyone help me in this regards.

my design file name is: my_bus(entity name)
my test bench name is: tb_bus(entity name)

After compiling all my files, I've included my design entity as "use work.my_bus.all;" in my test bench file apart from "library ieee;" and "use ieee.std_logic_1164.all"

I got this error.

ncvhdl_p: *E, SNLEBI: Same name for library and entity not allowed in binding indication

this error was generated on line "use work.my_bus.all;"

there was also a suggestion saying that use -relax option while compilation but that did not work out.

I tried using just "use work.all;" even this didn't work out.

Can anyone help me in this regards of how to overcome this error. or wat has caused this error.

Thanks in advance,
Jalli


Originally posted in cdnusers.org by jaally
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    Hi Jalli I think there is no need to include that line ("use work.my_bus.all;"). Just remove that line and rerun it. I think that will solve your problem.


    Originally posted in cdnusers.org by vlsi_dude
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    Ok dude,

    Thanks but I got the solution earlier.

    Rgds,
    Jalli


    Originally posted in cdnusers.org by jaally

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