dynamically assigning the drivers for a virtual seq

Hi there, I'm having some sort of "constraint" problem, which some of you might have the answer to. The Scenario is the following, I use a virtual Sequence driver to drive frames onto a dynamic number of phy drivers. The goal is to be able to write a virtual sequence, which can be told on which phy it shall inject its sequences:

extend virtual_seq_driver
{
    !phy_driver[4] : list of phy_driver_u;
};

extend sve
{
    virt_seq_driver : virtual_seq_driver is instance;
    connect_pointers() is also
    {
        for i from 0 to virtual_seq_driver.phy_driver.size() - 1 do
        {
            virt_seq_driver.phy_driver[i] = pointer_to_list_of_phy_drivers_somewhere[i].driver;
        };
    };
};

sequence virt_seq using created_kind = virtual_sequence_t, created_driver : virtual_seq_driver;

extend virt_seq
{
    !phy_seq : some_phy_seq;
        keep phy_seq.driver = driver.phy_driver[phy_seq.seq_port_no - 1];
    -- ^^ This keep constraint results in a contradiction, because the seq_port_no is not properly constrained
};

extend some_phy_seq
{
    keep gen (seq_port_no) before (driver);
    seq_port_no : uint (bits:4);
    keep soft seq_port_no == 1;
};

The code above does not really work, as seq_port_no is used with a somehow totally unconstraind value (actually PGen tries to use a range). If I comment the constraint on the driver and constrain seq_port_no while calling the sequence with

extend MAIN virt_seq
{

    do phy_seq keeping
    {
        .seq_port_no == 1;
        .driver == driver.phy_driver[.seq_port_no - 1];
    };
};

everything works peachy and I can constrain the sequence dynamically to any Phy Port I want to use. How can I constrain it properly, so I don't have to constrain the driver every time I driver the sequence?

cheers for any solution