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Accesing Signal in Mixed HDL environment

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Hi..... I have VHDL DUT and Verilog Testbench. I am writing an eVC for this environment. I want to access my vhdl DUT top level signal. I am writing signal map unit in 'e' for binding the e ports with DUT signals(VHDL). It's giving me error while generating the test signal in specman that: Doing setup ... Generating the test using seed 1... *** Error: The type of HDL object 'tb_top.DUT_top.addr' is unknown. Check if the hdl_path() attribute is set. The HDL object may be of an unsupported type, or trying to access through Verilog PLI to a VHDL object (If so - make sure the agent() attribute isset properly). To access composite System Verilog types use indexed port Here, addr are my DUT top level port (VHDL). Then I have made changes in signal map unit, i have written: keep agent() == "Vhdl"; as per specman mannual. After this again it is giving error: Generating the test using seed 1... *** Error: ERR_DID_NOT_FIND_ADAPTER: Unresolved adapter identification name 'Vhdl'. When you set this condition to a severity of WARNING or IGNORE, then the NULL_SIM adapter is used instead. Please help me. Thanks


Originally posted in cdnusers.org by vlsi_dude
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  • Hi Hannes,

    I am still getting the same error.

    I will again explain my problem:
    My Testbench name is tb_top.v and DUT name is DUT_top.vhd.
    I have instantiated the specman_reference component in DUT_top.vhd file i.e. in DUT top file.
    Now i want to access the DUT signals i.e. signals in file DUT_top.vhd.

    I am using "irun" command:

    "irun DUT_top.vhd tb_top.v env.e -snvlog -top tb_top -design_top DUT_top -access +rwc -nowarn -clean -v200x -gui"

    If anything else i have to add in this please suggest me and also i am not getting that how to create multiple stub file for both vhdl & verilog using "irun" command.

    Thanks


    Originally posted in cdnusers.org by vlsi_dude
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  • Hi Hannes,

    I am still getting the same error.

    I will again explain my problem:
    My Testbench name is tb_top.v and DUT name is DUT_top.vhd.
    I have instantiated the specman_reference component in DUT_top.vhd file i.e. in DUT top file.
    Now i want to access the DUT signals i.e. signals in file DUT_top.vhd.

    I am using "irun" command:

    "irun DUT_top.vhd tb_top.v env.e -snvlog -top tb_top -design_top DUT_top -access +rwc -nowarn -clean -v200x -gui"

    If anything else i have to add in this please suggest me and also i am not getting that how to create multiple stub file for both vhdl & verilog using "irun" command.

    Thanks


    Originally posted in cdnusers.org by vlsi_dude
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