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Running e-SV together

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Hi,
I Want to test an uVC written in SV class based with the Help of a Shareware eVC. I want to have my uVC Master talking to eVC slaves.How can i do this ??

Thanks  & Regards,
Ramesh Pal


Originally posted in cdnusers.org by ramesh_pal_yadav

  • Hi,

    You can do this using method ports.

    Please refer to the IPCM guidelines, which has the concept explained better.
    In the section Universal Reuse Methodology -> Mixed Language Reuse Methodology, you will find description and couple of examples on interfacing 'e' with System Verilog.

    Thanks & Regards,
    Nilay Goyal
    www.einfochips.com


    Originally posted in cdnusers.org by nilaygoyal

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