IEEE Working Group Announces Updated 1647-2008 e Language Standard

Dear Specmaniacs,

First, full disclosure: my name is Joe Hupcey, and I'm the marketing person for Specman, Incisive Enterprise Simulator, and the "Trailblazer" program many of you have heard about.  Before going
over to "the dark side" (marketing), I worked as an EE in FPGA design, EDA tools for FPGAs, then ASIC verification. However, since I've been a marketing guy for ~8 years now, I will not be offended if you take everything I've written below with a grain of salt. ;-)

That said, based on some very positive feedback from recent conversations with Specmaniacs, I believe the following will be of interest to this forum.

With the arrival of the IEEE 1647-2008 revision to the e language standard, I was inspired to try to take a snapshot of e language usage today. Here are some interesting stats I uncovered:

* There have been over 5,500 tape outs with the e language

* It is estimated that there are >150 million lines of e code

* e usage has increased every year since e was introduced (measured by license count and new projects)

* e is used by 1000's of engineers who are already linked in several on-line communities (the old Yahoo Group and here at CDNusers.org)

* There are over 130,000 workstations running e-based tools today

* There are >1500 reusable e components developed by customers and partners alike.

* Over 250 independent engineering consultants provide e language verification services

And last but not least:
* e code is typically 3x more compact than any other solution


If you've read this far, you are a true Specmaniac!  Hence, while I have the floor, allow me to post some FAQs and corresponding answers that I've seen come up in the user community over the past year.

Q: What are the top 3 advantages of e/Specman Elite over any other verification solution (so I can remind myself, and inform curious colleagues)?

A: Recall e's structural benefits over any other language, which can be summarized by the statement that "e was purpose-built from the ground-up for verification", and by the top three sub-points:

* Easiest extendibility with AOP, with automatic type handling, and unique language extension macro support for customized modeling yielding an average 3x less lines of code versus other solutions

* Built-In Safety with an "Infinity Minus" approach to stimulus generation – i.e. "assume nothing" by exploring as much of the DUT as possible through maximum randomization, which is a very efficient approach for bug finding.

* e / Specman was built as a generic verification platform, so you can easily mix & match Verilog, VHDL, SystemVerilog, software (C, C++, assembler), SystemC, proprietary HDLs, Matlab, analog (SPICE netlists or A-HDLs), Acceleration/Emulation elements, even post-silicon setups, all together to unearth hard to find cross-domain bugs.


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Q Why should I continue to use e when SystemVerilog is clearly the "next big thing"?, and the related question, "Why does Cadence continue to invest in e-related technology?"

A: The answer to both questions is simple: because e language usage is growing.

If you are an end-user, and are not using e today, given the growing volume of e VIP you will likely see e-based VIP of some form in your career either directly, or connected to your non-e environment with OVM "plug & play" capabilities.  The vast majority of existing e users we see have decided to continue to use e given its strengths (see above) and its successful track record, as well as evaluate SystemVerilog and SystemC for some tasks.  In terms of daily engineering operations, since eRM and OVM have "plug and play" interoperability, and the e-SystemC connection is very mature, and since Incisive Enterprise Simulator (IES) supports all IEEE standard languages, there are no technology barriers to using multiple languages. (In short, it's a "multi-language world" -- no single language can do it all, so Cadence supports all IEEE languages in parallel and ensures they interoperate well.)

Elaborating on Cadence's motives: the company's continued investment in e technology is purely about money and customer commitments. e-based license usage – whether it's from IES, stand-alone Specman + a 3rd party simulator, or e-specific VIP sales – is growing in both the existing customer base, and in over 10 new companies each year since the Cadence-Verisity merger over 3 years ago.

Furthermore, Cadence respects our customers' ongoing use of the e language by supporting their needs and providing them new, best in class technologies. In return, these customers continue to rely on Cadence as a primary provider of their verification solutions.  Hence, Cadence continues to invest in e language-related technology in parallel with developments in all other IEEE standard languages.  As attendees of the "ClubT" regional meetings over the past 2 years
can attest, Cadence R&D enthusiastically continues to partner with customers on the advanced "Trailblazer" program.


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Q: What is Cadence doing to invest in and advance e-related technology?

A: Due to the maturity, stability, and popularity of the e language, it provides the perfect development platform for some of Cadence's advanced verification tools and flows.  Specifically, for the past 2 years Cadence has been funding the "Trailblazer" program, whose main objective is to partner key customers and Cadence R&D to maintain a 5 year technology lead over all other solutions.  The program's focus is in the areas of increasing automation, supporting the scalability
needed for the >= 1 billion logic gate designs coming around the corner, and multi-domain verification (HW/SW and mixed-signal). This includes:

* Investments in core engine technologies like the recently announced aspect-oriented stimulus generation technology (nicknamed "IntelliGen" -- recall these articles:
http://www.scdsource.com/article.php?id=48 and
http://www.cadence.com/company/newsroom/press_releases/pr.aspx?xml=120307_enterprise_verification

* New advances in eRM and the Plan to Closure methodology

* Leveraging Specman-originated technologies in our whole flow (including mixed-language and pure SystemVerilog-based OVM plug and play flows).


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Q: Will Cadence donate more e language technology to the IEEE 1647 working group?

A: Yes. Cadence's policy is to donate all e language technology to the IEEE 1647 Working Group without exception and without any restrictions.  In fact, the technology flow seems to be more of
a "pull" from the Working Group, where the members typically decide which e language elements have been sufficiently market-proven to be considered in a given revision of the standard.

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Q: My company has a lot of e code / eVCs I want to see "protected" by the IEEE 1647 standard. How do I sign-up for the IEEE 1647 Working Group to ensure new features important to my work are captured in future revisions of the e language standard?

A: As per the prior post from Andy Piziali, anyone can sign up on-line: http://www.ieee1647.org/join.html  Meetings are typically held (electronically) once a month, and
attendance at 3 of the last 4 meetings is required to earn/maintain voting status.