I want to do a HAL analysis on VHDL design.What are the procedure and steps for that?/
Please tell me
You can use cadence quick help for more explanation: nchelp ncvhdl_p LIBNOM
The logical library name indicated is not mapped to a design library.
Section [11.2] of LRM [87 & 93]. A user option file entry of the form:
must be present for each logical library name L.