Stats

  • Locked Locked
  • Replies 1
  • Subscribers 50
  • Views 13184
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

C-to-Silicon Error (CTOS-13043)

Romen
Hi,

I'm using C-to-Silicon to generate a RTL model for a CAVLD module from a H.264/AVC video decoder. During the build step, at the end of the process, I'm obtaining this error:


Saving design 'cavld_core' to cavld_core/elaborated. Writing Post-Build SystemC Simulation Model:

write_sim -type systemc -suffix _post_build_sc -birthday -recursive -o ./model /designs/cavld_core/modules/cavld_core.

Writing Post-Build Verilog Simulation Model:

write_sim -type verilog -suffix _post_build -birthday -recursive -o ./model /designs/cavld_core/modules/cavld_core.

Writing Verification Wrapper:

write_wrapper -o ./model/cavld_core_ctos_wrapper.h /designs/cavld_core/modules/cavld_core.

ERROR (CTOS-13043): Internal error encountered while executing build:

Expression [op == callOp || op->isControl()] returned false in file bstValidator.cpp at line 1135.

0x90a8c92: _ZN9CallStack4initEv
0x90a8e43: _ZN9CallStackC1Ev

0x90b63ba: _ZN5Error6formatERPc

0x90b6917: _ZN5ErrorC1Ejz
...

...

...

Error in processing command build

 

It would be most appreciated if someone can help me with this issue.

Thanks in advance for your help.

Best Regards.

Romén.
Parents

  •  Hi Romen,

    Sorry that you are seeing a crash. We continuosly strive towards making the CtoS more robust and appreciate any help we can get from customers.

    You are probably predicted what I am going to ask next: Would it be possible for you to contact Cadence customer support so that someone can work with you?

    If that is not an option, here are some tips:

    - Does your design pass simulation? Do you have a good SystemC (or any other language) TB to verify your DUT (design under test)? You can catch a lot of coding errors during simulation. You would be surprised how many customers simply write the SystemC DUT, don't simulate at the SystemC level, generate RTL from CtoS and do full simulation at the RTL level... IMO, those people are missing the point. You want to do all functional verification at the SystemC (high-level) and re-use the high level TB to verify the generated RTL.

     - Run with 'build -verbose'. It will print debug messages as it parses your design. You might be able to figure out which line it is having a problem with.

     NOTE: Please post all your future TLM-D (CtoS) questions to:

     High Level Synthesis Forum

    /forums/90.aspx

     

    Regards
    Rajesh

     

Reply

  •  Hi Romen,

    Sorry that you are seeing a crash. We continuosly strive towards making the CtoS more robust and appreciate any help we can get from customers.

    You are probably predicted what I am going to ask next: Would it be possible for you to contact Cadence customer support so that someone can work with you?

    If that is not an option, here are some tips:

    - Does your design pass simulation? Do you have a good SystemC (or any other language) TB to verify your DUT (design under test)? You can catch a lot of coding errors during simulation. You would be surprised how many customers simply write the SystemC DUT, don't simulate at the SystemC level, generate RTL from CtoS and do full simulation at the RTL level... IMO, those people are missing the point. You want to do all functional verification at the SystemC (high-level) and re-use the high level TB to verify the generated RTL.

     - Run with 'build -verbose'. It will print debug messages as it parses your design. You might be able to figure out which line it is having a problem with.

     NOTE: Please post all your future TLM-D (CtoS) questions to:

     High Level Synthesis Forum

    /forums/90.aspx

     

    Regards
    Rajesh

     

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.