I want to know if I compile one systemverilog package in a library, then in vhdl side, can it access the element in this package ?
For example .
const int a =10;
// //file tb.vhd
I compile it by
'irun -makelib pkg_lib pkg.sv -endlib'
'irun -reflib INCA_libs/pkg_lib tb.vhd '
I got the error complaining the package pkg cannot be found in the library. I want to know whether it is impossible to access a systemverilog package from the VHDL code , or I missed something ? Thanks a lot !
This isn't currently possible, but I'm collecting requirements from users and am working on a solution. Please can you let me know the details of what you need to access from the VHDL package? Feel free to PM me or email to email@example.com if you'd prefer not to discuss the details in public.