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  3. Is it possible for VHDL to use a verilog/systemverilog package...

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Is it possible for VHDL to use a verilog/systemverilog package ?

Xinwei
Xinwei over 12 years ago

 Hi all,

 I want to know if I compile one systemverilog package in a library, then in vhdl side, can it access the element in this package ? 

For example .

//file pkg.sv

package pkg;

const int a =10;

endpackage

 

// //file  tb.vhd

library pkg_lib;

use pkg_lib.pkg.all;

......

 

I compile it by

'irun -makelib pkg_lib pkg.sv -endlib'  

'irun -reflib INCA_libs/pkg_lib tb.vhd '

 

I got the error complaining the package pkg cannot be found in the library.  I want to know whether it is impossible to access a systemverilog package from the VHDL code , or I missed something ?  Thanks a lot !

Best regards, 

Xinwei 

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  • Xinwei
    Xinwei over 12 years ago
    Hi Stephen and Jason,
     
    Thanks for your reply.
     
    By the way, I have another question related to the package access (Or It is not only for pkg, but for the common access).
     
    For example,
     
    I have a source file src.sv that has a line "import pkg1::*;".   The pkg1 is defined in the file pkg1.sv.  Then I compile it by the following way:
     
    irun -c pkg1.sv -makelib lib1 src.sv -endlib
     
    In this situation, pkg1 is invisible for src.sv that compiled into lib1.  I know how to workaround this problem. But I still want to ask do you do this on purpose or maybe you can improve this to make pkg1.sv visible to src.sv even if it is compiled into a library.
     
    Please correct me if I misunderstand anything.
     
    Thanks and best regards,
    Xinwei
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  • Xinwei
    Xinwei over 12 years ago
    Hi Stephen and Jason,
     
    Thanks for your reply.
     
    By the way, I have another question related to the package access (Or It is not only for pkg, but for the common access).
     
    For example,
     
    I have a source file src.sv that has a line "import pkg1::*;".   The pkg1 is defined in the file pkg1.sv.  Then I compile it by the following way:
     
    irun -c pkg1.sv -makelib lib1 src.sv -endlib
     
    In this situation, pkg1 is invisible for src.sv that compiled into lib1.  I know how to workaround this problem. But I still want to ask do you do this on purpose or maybe you can improve this to make pkg1.sv visible to src.sv even if it is compiled into a library.
     
    Please correct me if I misunderstand anything.
     
    Thanks and best regards,
    Xinwei
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