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vhdl-verilog interoperation ?

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Can I force or probe a signal in vhdl module from verilog top testbench?
I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

 


Originally posted in cdnusers.org by hubertx
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  •  Hi Rajan,

    I am assuming that you are attempting to create the force by directly assigning a value to the signal using an out-of-module reference (OOMR) path from within a verilog procedural block.  As you've probably discovered there is no way to do the above in verilog code using an OOMR.  This is because any OOMR path that begins with a verilog instance must end in a verilog instance.  That's not to say, however, that it can't be done, it just can't be done within the verilog coding.

    The way to do this is by using the tcl interface to ncsim.  Be aware that you will also need to insure that you have elaborated the design with write access.  The tcl argument to execute the force is as follows, depending on whether the signal is one or multiple bits: 

    force path.to.the.signal = '0'

    force path.to.the.vector = "1001101"

    Hope that helps.

    Mickey

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  •  Hi Rajan,

    I am assuming that you are attempting to create the force by directly assigning a value to the signal using an out-of-module reference (OOMR) path from within a verilog procedural block.  As you've probably discovered there is no way to do the above in verilog code using an OOMR.  This is because any OOMR path that begins with a verilog instance must end in a verilog instance.  That's not to say, however, that it can't be done, it just can't be done within the verilog coding.

    The way to do this is by using the tcl interface to ncsim.  Be aware that you will also need to insure that you have elaborated the design with write access.  The tcl argument to execute the force is as follows, depending on whether the signal is one or multiple bits: 

    force path.to.the.signal = '0'

    force path.to.the.vector = "1001101"

    Hope that helps.

    Mickey

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